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Manual Installation and Maintenance of SDH/SONET, ATM, xDSL, and Synchronization Networks

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Full Name Comment goes here. Are you sure you want to Yes No. Be the first to like this. No Downloads. Views Total views. Actions Shares. Embeds 0 No embeds. No notes for slide. If you want to download this book, click link in the last page 5. You just clipped your first slide! Clipping is a handy way to collect important slides you want to go back to later. Jitter and Wander Control. Notes Includes bibliographical references and index. View online Borrow Buy Freely available Show 0 more links Set up My libraries How do I set up "My libraries"?

La Trobe University Library. Borchardt Library, Melbourne Bundoora Campus. Open to the public ; Macquarie University Library. Open to the public ; TK Monash University Library. University Library. Open to the public. None of your libraries hold this item. Found at these bookshops Searching - please wait We were unable to find this edition in any bookshop we are able to search. A plurality of provider switches may be connected to each other using any topology.

Alternatively, the network may comprise only provider edge switches whereby a plurality of provider edge switches are connected in a ring topology. The provider switch comprises computer readable storage medium for storing program code and data which may include any suitable memory means including but not limited to magnetic storage, optical storage, CD-ROM drive, ZIP drive, DVD drive, DAT cassette, semiconductor based volatile or non-volatile memory, biological memory devices, or any other memory storage device.

Software operative to implement the functionality of the present invention is adapted to reside on a computer readable medium, such as a magnetic disk within a disk drive unit or any other volatile or nonvolatile memory.

Installation and Maintenance of SDH/SONET, ATM, xDSL, and Synchronization Networks

The software adapted to perform mechanisms and methods of the present invention or any portion thereof may also reside, in whole or in part, in the static or dynamic main memories or in firmware within the processor of the switch i. Classical Ethernet networks use copper for the physical interface i. Layer 1 or PHY communication links between nodes and for shared media between two or more ports i. Data rates of 10, and Mbps are available on copper based Ethernet connections. Copper based Ethernet transmits packets asynchronously, sending packets out onto the line only when it needs too.

The remainder of the time, the copper line is idle and is not used at all. In contrast to copper Ethernet, only point-to-point connections are used in optical Ethernet networks. Optical Ethernet links use coding for transmitting the bits over the point-to-point optical fiber communication links. In each of these Ethernet schemes, physical coding bits are always transmitted on the communication line even when there are no packets to send. In optical Ethernet, idle sequences are transmitted when there are no packets to transmit.

Thus, in optical Ethernet, there is perpetual activity on the optical lines. Perpetual transmission activity on the optical communication line means that there is always an optical Ethernet signal available from which a clock can be recovered. The clock synchronization mechanism of the present invention utilizes this to 1 extract clock signals from the received optical Ethernet signals which may have different rates, 2 perform rate adaptation whereby all the clock signals are converted to a common rate, and 3 select one of the clocks to be used to generate a plurality of Ethernet clock signals that are used to generate Ethernet output transmit signals.

A block diagram illustrating an example clock synchronization circuit of the present invention is shown in FIG. The clock synchronization circuit, generally referenced , comprises a clock recovery circuit , rate adaptation circuit , selection means and clock regeneration circuit In operation, one or more optical Ethernet signals received over optical Ethernet communication links are input to the clock recovery circuit.

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Other external or internal clock sources may also be input to the clock recovery circuit as well. The clock recovery circuit functions to extract the clock from each of the received optical Ethernet signals. This may be accomplished in any of several ways as described infra. Clock recovery techniques for both copper and optical Ethernet signals are well known in the art. The clock signals output of the clock recovery circuit and the external and internal clock signals are input to the rate adaptation circuit. It is noted that each of the input clock signals may have a rate independent of the rate of the other clock signals.

The rate adaptation circuit functions to translate the rate of each of the input clocks to a common rate that is shared across all input clock signals.

SONET/SDH Basics, Devices, Structure, Operation, Frame, Network and Applications

Thus, the rate adaptation circuit functions to convert all the input clock signals to output clock signals wherein the rate of each output clock signal is the same. It is appreciated, however, that the invention is not limited to this common rate as any common rate may be used depending on the particular implementation. The common rate clocks output of the rate adaptation circuit are input to a selection means, e.

Question e-book or training material for ATM & Syncronization plan

A clock source select signal determines which of the common rate clocks are to be selected. Normally, the clock source having derived from the highest quality clock source is selected as the primary clock. The controller or other higher layer entity has or is provided knowledge of the clock signals available to the device. For example, if one of the external clock sources comprises a high quality clock provided by a service provider e.

The primary and secondary clock signals are input to the clock regeneration circuit which is operative to perform all necessary clock signal processing functions such as phase locking, holdover, smooth switchover, jitter attenuation and wander filtering. Generating and distributing a quality output clock signal requires performing several processing functions on the clock signal at the Ethernet rate. These include jitter attenuation, holdover, wander filtering and smooth clock switchover.

Holdover is a function used when the clock source is absent and is adapted to hold the last clock frequency with same defined maximum drift as defined in the well known Stratum 3 standard. Smooth switchover is implemented so that switching from one clock to another will not cause a disruption of the clock phase, thus avoiding any bit errors. A filter is used to achieve high jitter performance, i. A wander filter improves wander performance by achieving a very low rate of clock phase change.

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The clock regeneration circuit is also operative to generate any required Ethernet clock signals and external or internal clock signals using the primary or secondary clock signals as the reference. The clock source select signal determines whether the primary or secondary clock is used by the clock regeneration circuit to generate the output clock signals.

To achieve this, the mechanism of the invention distributes the clock using the physical layer of optical Ethernet. Only a single node needs to receive the quality external clock which is then used to synchronize the entire network. Each node in the network implementing the present invention selects one clock from the various different sources to synchronize all communication links connected to it.

Each node is operative to recover the clock from all optical links connected to it and to use any of these clocks for distribution to the network. Further, each node is operative to perform jitter attenuation of the particular clock used for distribution.


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In addition, the invention comprises means for passing synchronization status messaging SSM messages between nodes for communicating clock quality information between nodes. Conventional Ethernet PHY devices do not normally provide the recovered clock as an output. Therefore, the mechanism of the invention overcomes this by passing the signal from each serial link through a repeater device that copies the Ethernet signal sending one signal to the MAC for data recovery and the second signal to the clock recovery circuit FIG.

Note also that unlike TDM rates 8 kHz there is no common rate that can be used on all Ethernet interfaces. Therefore, the clock regeneration circuit FIG. As described supra, the clock synchronization mechanism of the invention implements synchronization status messaging SSM between nodes whereby information about the quality of the clock signal is transferred from one node to another. It is noted that there are no headers in Ethernet that are dedicated to SSM. Therefore, the invention provides two alternative embodiments for implementing SSM in an Ethernet network.

The first uses special in band packets containing the SSM information. A diagram illustrating the message format of an in band OAM packet adapted to convey clock synchronization status information is shown in FIG. The remaining 4-bit field is reserved and a padding field is used to fill the packet to 64 bytes. Note that implementing OAM packets for SSM messaging distribution requires the modification of several packet processing entities including the network processor, Ethernet switch, etc.

Note that this scheme of sending SSM information has the advantage of being a physical layer attribute that does not require modification of packet processing entities such as the network processor, Ethernet switch, etc. A block diagram illustrating an example 1 G Ethernet clock synchronization circuit of the present invention for distributing a TDM clock is shown in FIG. The example implementation described is capable of handling four 1 G optical Ethernet links.

This example circuit is presented for illustration purposes only and it not intended to limit the scope of the invention as clock synchronization circuits adapted to handle any number of links may be constructed by one skilled in the art using the principles of the present invention. The four 1.


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  7. The four MHz clock signals are input to the clock divider circuit in the clock rate adaptation block The clock divider functions to divide the each of the four clock signals down to a common rate of 8 kHz. The four common rate clock signals are input to multiplexer Also input to the multiplexer are two 8 kHz clock signals input from the CES interface card A clock source selection signal determines one of the six common rate clock signals to be the primary clock and one to be the secondary clock. The selection would be made to choose the input signal i. The clock source selection signal selects either the primary or secondary clock to use to generate the output clocks, i.

    The 25 MHz clock is passed through a jitter attenuation circuit for filtering out jitter in the clock signal. Note that this function may be performed by the DPLL or other equivalent circuit. The output of the jitter attenuation circuit is multiplexed with a 25 MHz LO The 1. Note that the 25 MHz clock output of the multiplexer may also be input to the network processor where it is used to synchronize the data output of the network processor.

    This example circuit is presented for illustration purposes only and it not intended to limit the scope of the invention as clock synchronization circuits adapted to handle any number of inputs e. The operation of the 1 G portion of the synchronization circuit is similar to that of the circuit of FIG. The 24 1. The 24 MHz clock signals are input to the clock divider circuit in the clock rate adaptation block The clock divider functions to divide the each of the 24 clock signals down to the common rate of 8 kHz.

    The 24 common rate clock signals are input to multiplexer The two The two WAN common rate clocks are input to multiplexer The two LAN common rate clocks are input to multiplexer The 2. The TDM common rate clocks are input to multiplexer The backplane clock source may comprise an Ethernet line card, internal clock source, etc. Note that although these clocks are already the common rate of 8 kHz, their phase may vary since they are derived from sources asynchronous with one another.

    A clock source selection signal selects one of the common rate clock signals to be the primary clock and one to be the secondary clock. The selection is preferably made so that the input signal i.


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    4. The clock source selection signal selects either the primary or secondary clock to use to generate the output clocks, including the 25 MHz clock, 2. Rx and Tx 1. The LAN clock is input to multiplexer along with the The output of the multiplexer is input to the network processor where it is used to synchronize the data output of the network processor.

      The LAN clock is also input to multiplexer along with the As described supra, the invention provides several alternative implementations of the 1. Any of the following implementations may be used where the particular implementation used will likely be based on cost, board space and power constraints.

      A block diagram illustrating a first alternative 1. In this clock recovery implementation, generally referenced , the Rx Ethernet signal is input to a repeater buffer which duplicates the Rx Ethernet signal into two 1. This clock signal is then input to the clock rate adaptation circuit. A block diagram illustrating a second alternative 1. A block diagram illustrating a third alternative 1. In this clock recovery implementation the Rx Ethernet signal is input to a clock recovery module The clock recovery module is configured to pass the 1.