The simulator computes in- module or board so that they can be easily manipulated ductance and capacitance matrices for the segment, on a per component bias. After all the segments are modeled, the sub- are placed into "partitions? It is in subcircuit form or defined using Thevenin equivalent through the creation of partitions that complex systems circuits from user supplied characteristics and the can be built using the tool. All of the simula- titions include interconnect technologies, heat ex- tion management and post processing is handled by the changers, and connectors.
A netlist corresponding to trade-off tool and performed concurrently with size, the partition under design, a group of partitions, or a routing, cost, reliability, testability, and thermal design larger than that under consideration is an op- analyses. Tools have been de- placed inside of each other to build systems and study veloped that give advice on specific "views" such as trade-offs associated with alternative distributions of reliability, manufacturability, or power distribution see components among system interconnects.
The hier- - for examples. Personal computers are Is,,,c V I SPICE built using highly integrated usually single CPU frequency sweep [ trans ent ana ys s systems with much smaller power dissipations, lower costs, and poorer performance than high-end systems. Bandwidths Delays These market segments are making functional parti- attenuation tioning trade-offs. Critical net delay and bandwidth attenuation evaluation. A In light of these trade-offs, the objective of this study segment is defined in the model as the length of line between two is to determine the optimal number of chips necessary nodes i.
In this 3. Example Results article we are concerned with multichip modules MCMs. Direct chip attach methods used in MCMs Trade-off studies for numerous multichip systems per- include peripheral bonding approaches such as wire- formed using the tool described in the last section have bonding and tape automated bonding TAB , and area been published previously -.
The comparison in this systems since die can be placed closer together and study has been made in the context of a multichip mod- higher performance systems since the effective induc- ule MCM. The results presented in this article focus tance associated with the chip bonds is reduced and line on a comparison of cost including module assembly, drivers can potentially be smaller.
On the other hand, test, and rework to assess the overall applicability of area array bonding requires extensive die preparation one bonding format over the other. Additional trade- today, this is only economical before wafers are diced offs electrical, thermal, and size for this comparison and the infrastructure to support peripheral bonding is of peripheral and area array bonding are presented in considerably greater than that for area array i.
Real-World R&D: Jumping the Product Generation Gap
Putting a large amount of functionality cost, test, mad rework must be performed. Analyzing into a single chip may provide electrical performance system costs while neglecting the chips will not gener- and system size advantages, but often results in large ally lead to a correct relative cost comparison between die with low yields and high costs. Alternatively, realiz- packaging alternatives. Similarly, analyzing chip costs ing the same functionality using a large number of small to meet a specified functionality without considering die, results in less cosily die, at the expense of a larger the cost of packaging and the costs associated with test system size and possible performance degradation.
In and rework can be equally misleading; i. For an area array bonded die, the die area is given by the maximum 3. A the die is computed. The yield of die on the wafer was larger signal to ground ratio is allowed for area array computed using Murphy's yield law  with a fixed bonding due to the lower effective inductance associated defect density, with flip chip bonding due to shorter bond lengths.
The size estimations for peripheral and area array die are similar where D is the average defect density defects per unit to the formulations developed in .
Research: System Focus vs. the Traditional Pipeline
For a peri- area on the wafer. The number-up on the wafer was pherally bonded die, the area is given by the maximum computed assuming a fixed minimum spacing between of two limitations: die 50 mils. The methodology used to determine the Multichip Module MCM cost for various partitioning and bonding approaches. In all cases the chip or gate set that was replacing yieldwd with the incoming die yield. The studied was assumed to be part of a processor module wafer or die cost is computed at the end of each step that included an additional large chip an ASIC of some shown in Figure 6 using the relation, type and ten SRAMs.
The characteristics of the chips in the module are given in Table 1. The number of gates in the chip in this using the trade-off analysis tool described in Section case is approximately 2,, 0. Included in this analysis is a detailed The results for this case are then generated by fixing estimation of module costs, along with the cost of the number of gates in the CPU at the above value and assembly, test, and repair as discussed in . The results of this analysis are shown in Figures 7 3.
(PDF) Multichip systems trade-off analysis tool | Peter A. Sandborn - gyqacyxaja.cf
Z Results through Characteristics of the test module used for the example in this article. The yield corresponds to the yield of the die at the start of assembly i.
The critical assumptions used to generate the results in this article are included in Table 2. Critical analysis assumptions used to generate the trade- off results presented in this article. Bond Pad Pitch peripheral 4 mils Min. Defects Added by Wafer Bumping 0. Feature Size on Die 0. Power dissipation per CPU chip and totalpower dissipation for the set of chips the CPU is divided into the power dissipations of all Quantity 50, modules other components in the MCM are included in the Total Module curve.
SingleCPU die area and core die area as a functionof the Fig. Completed M C M cost. Both the rray peripheral format chip and the area array format chip track the core area. The area array chip is smaller than ' the peripheral chip due to the extra area required for the redistribution of connections from inside the core of the die to its periphery. Figure 10 shows that the difference in cost per die for peripheral and area array format die is minimal. When 0 9 9 i , : only one die is used, the peripheral die cost is actually 0 2 4 6 8 10 less than the area array die cost because the cost of Number o f C P U Chips bumping the wafer containing the area array die is Fig.
Single die cost as a function of the number of chips the CPU amortized over relatively few working die per wafer is divided into. Figure 8 shows the power dissipation per chip than peripheral die, more than offsets the bumping cost Per Die and the total power dissipation of all the chips incurred by each die.
A chip's power dis- terest is not the cost of a single die but the cost of the sipation is proportional to its number of gates, so power completed multichip module and when assembly, test, dissipation drops as the number of gates drops. The and repair effects are considered. The result is a net increase in the assumed.
The figure shows that for this application, the 2. Nagesh, D. Miller, and L.
Read Now Conceptual Design of Multichip Modules and Systems (The Springer International Series in
Moresco, "A Comparative optimal number of chips into which to divide the func- Study of Interconnect Technologies," Proc. With the ex- Gajsld and R. The results in Figure 11 are ap- 4. Birmingham, A.
Gupta, and D. Siewiorek, Automating plication specific. Dewey and S. MCM designs, but it cannot be considered in isolation. Bortolazzi and K. Several quan- Edmond, A. Gupta, D. Siewiorek, and A.
These quantities include the wafer test 8. Exensions to this work should concentrate 9.
Sandbom and H. International Symposium on Microelectronics in order to obtain more accurate comparison results. ISHM , pp. International Conference on Advances in In- 4. This article described a software tool that performs EleventhInternational trade-off analysis for multichip modules and systems. Electronics Manufacturing TechnologySymposium, pp.
Sandborn, H. Hashemi, and L. Sandborn, M. Abadir, and C. Notes Alternatively the model could be divided into more general system Dobberpulal, et al. Dehkordi and DW. Bouldin, "Design for Packagability: 2. References Williams and N. Neugebauer and R. Carlson, "Comparison of Wafer , Dec. Abadir, A. Parikh, L. Bal, C. Our domain expertise in rugged 3D packaging eliminates SWaP versus performance compromises. Custom Microelectronics Applications.
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